1. Field of the Invention
The present invention relates to an analog amplifier and an analog filter for amplifying an analog signal. More particularly, the present invention relates to an amplifier and a filter for logarithmically controlling a variable gain and a cutoff frequency according to a digital control code.
2. Description of the Related Art
FIG. 1 depicts an analog filter structure according to the related art.
Referring to FIG. 1, the analog filter is constructed by coupling a plurality of first or higher order filter stages 100 (e.g., Stage 1, Stage 2, . . . , Stage n). A highpass feedback stage 110 is coupled between a first amplifier stage and an (n−1)-th amplifier stage, to cancel noise in a Direct Current (DC) component and remove a DC offset.
Although not illustrated, each filter stage 100 includes an operational amplifier, a variable resistor, and a variable capacitor. A gain and a cutoff frequency are controlled by the variable resistor and the variable capacitor. That is, the gain of each filter stage 100 is determined by a ratio of an input resistance and a feedback resistance, and the cutoff frequency is determined in inverse proportion to a product of the feedback resistor and the feedback capacitor.
The variable resistor of the filter stage 100 includes two or more segments which combine short-circuit switches and resistors. The short-circuit switch is controlled by a digital code K. A resistor serial connection controlled digitally is in a binary structure such as 2R, 4R, 8R, 16R, . . . , 2nR (n is an integer), and a total resistance is linearly proportional to the digital code. The resistance of the variable resistors linearly changes according to the digital code K, and the cutoff frequency is proportional to a reciprocal of the resistance.
In a frequency domain, a frequency axis is typically represented on a log scale and a decibel (dB) unit indicating the gain is a log scale value. Accordingly, the variable resistance which linearly varies according to the digital code K has non linearity in the log domain. However, such non linearity degrades efficiency.
That is, as the digital code K decreases, the variable resistance rapidly changes on the log scale. By contrast, as the digital code K increases, the variable resistance slowly changes on the log scale. This degrades not only the efficiency but also the accuracy of the variable resistance in a high frequency band as shown in FIG. 2, and thus results in uncontrollable sections.
FIG. 2 is a graph showing a relationship of frequency and gain according to the related art.
Referring to FIG. 2, as the digital code K increases, the variable resistance slowly changes on the log scale. By contrast, as the digital code K decreases, the variable resistance rapidly changes on the log scale. As a result, an uncontrollable section of the cutoff frequency is generated.
When frequency variation is measured per digital code, the variation is jagged because of a quantization error in each variation section as shown in FIG. 3. Hence, the uncontrollable section arises even when the frequency axis is regarded linearly, rather than using the log scale.
FIG. 3 is a graph of a relationship of a digital control code and frequency according to the related art.
Referring to FIG. 3, because it is not easy to set the cutoff frequency and the gain using the dB, a complicated digital logic circuit is required to logarithmically convert the linear digital code if necessary.
For example, to control the gain on a 3 dB basis, when the variable resistance is set to 500, 707, 1000, and 1414, and the digital code value K of 0, 1, 2, and 3 (representable with 2 bits) is given for the four resistance values respectively, a logic circuit is required to convert the value K to logarithmic digital codes of 5, 7, 10 and 14, which are approximate values. Since the approximate value is subject to considerable error, the implementation increases the number of bits from 2 bits to 4 bits. If an additional reduction in error is desired, an additional increase in the number of bits is required.
To implement the digital logic, a relatively simple method converts the value using a Read Only Memory (ROM). However, when the cutoff frequency and the gain are converted at the same time, the combination increases geometrically and it is not easy to realize the method with a simple equation.
Therefore, a need exists for a filter and an amplifier for simply controlling the variable gain and the cutoff frequency logarithmically according to the digital code.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present invention.